The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Aug. 28, 2013
Applicants:

Mihailo M. Stojancic, San Jose, CA (US);

Gerald George Pechanek, Cary, NC (US);

Inventors:

Mihailo M. Stojancic, San Jose, CA (US);

Gerald George Pechanek, Cary, NC (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 7/12 (2006.01); H04N 11/02 (2006.01); H04N 11/04 (2006.01); H04N 19/80 (2014.01); H04N 19/42 (2014.01); H04N 19/436 (2014.01); H04N 19/59 (2014.01);
U.S. Cl.
CPC ...
H04N 19/0089 (2013.01); H04N 19/80 (2014.11); H04N 19/42 (2014.11); H04N 19/436 (2014.11); H04N 19/59 (2014.11);
Abstract

Apparatus and methods for scalable block pixel filtering are described. A block filtering instruction is issued to a processing element (PE) to initiate block pixel filtering hardware by causing at least one command and at least one parameter be sent to a command and control function associated with the PE. A block of pixels is fetched from a PE local memory to be stored in a register file of a hardware assist module. A sub-block of pixels is processed to generate sub-block parameters and the block of pixels is filtered in a horizontal/vertical edge filtering computation pipeline using the sub-block parameters.


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