The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2015
Filed:
May. 22, 2012
Seiichi Yoneda, Kanagawa, JP;
Jun Koyama, Kanagawa, JP;
Yutaka Shionoiri, Kanagawa, JP;
Masami Endo, Kanagawa, JP;
Hiroki Dembo, Kanagawa, JP;
Tatsuji Nishijima, Kanagawa, JP;
Hidetomo Kobayashi, Kanagawa, JP;
Kazuaki Ohshima, Kanagawa, JP;
Seiichi Yoneda, Kanagawa, JP;
Jun Koyama, Kanagawa, JP;
Yutaka Shionoiri, Kanagawa, JP;
Masami Endo, Kanagawa, JP;
Hiroki Dembo, Kanagawa, JP;
Tatsuji Nishijima, Kanagawa, JP;
Hidetomo Kobayashi, Kanagawa, JP;
Kazuaki Ohshima, Kanagawa, JP;
Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;
Abstract
An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits.