The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Jan. 25, 2010
Applicants:

Brent A. Anderson, Jericho, VT (US);

John E. Barth, Jr., Williston, VT (US);

Herbert L. Ho, New Windsor, NY (US);

Edward J. Nowak, Essex Junction, VT (US);

Wayne Trickle, Rochester, MN (US);

Inventors:

Brent A. Anderson, Jericho, VT (US);

John E. Barth, Jr., Williston, VT (US);

Herbert L. Ho, New Windsor, NY (US);

Edward J. Nowak, Essex Junction, VT (US);

Wayne Trickle, Rochester, MN (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/84 (2013.01); H01L 27/1087 (2013.01); H01L 27/10894 (2013.01); H01L 29/66181 (2013.01);
Abstract

Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer. One embodiment of the invention provides an integrated circuit for an embedded dynamic random access memory (eDRAM) comprising: a semiconductor-on-insulator (SOI) wafer including: an n-type substrate; an insulator layer atop the n-type substrate; and an active semiconductor layer atop the insulator layer; a plurality of deep trenches, each extending from a surface of the active semiconductor layer into the n-type substrate; a dielectric liner along a surface of each of the plurality of deep trenches; and an n-type conductor within each of the plurality of deep trenches, the dielectric liner separating the n-type conductor from the n-type substrate; wherein the n-type substrate, the dielectric liner, and the n-type conductor form a buried plate, a node dielectric, and a node plate, respectively, of a cell capacitor.


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