The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Jan. 24, 2014
Applicant:

Harris Corporation, Melbourne, FL (US);

Inventors:

Louis Joseph Rendek, Jr., Melbourne, FL (US);

Michael Raymond Weatherspoon, West Melbourne, FL (US);

Casey Philip Rodriguez, Indialantic, FL (US);

David Nicol, Melbourne, FL (US);

Assignee:

HARRIS CORPORATION, Melbourne, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2006.01); H05K 1/03 (2006.01); H05K 3/28 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H01L 24/83 (2013.01); Y10T 29/49156 (2015.01); Y10T 428/24917 (2015.01); Y10T 29/49144 (2015.01); Y10T 428/25 (2015.01); Y10T 29/49165 (2015.01); H01L 23/49894 (2013.01); H05K 1/0306 (2013.01); H05K 3/281 (2013.01); H05K 3/3436 (2013.01); H05K 3/3452 (2013.01); H05K 2201/0141 (2013.01); H05K 2201/10674 (2013.01); H05K 2203/063 (2013.01); H01L 2224/11422 (2013.01); H01L 23/3157 (2013.01); H01L 23/49822 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 24/94 (2013.01); H01L 25/0657 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/1148 (2013.01); H01L 2224/13021 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/94 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06568 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16145 (2013.01); H01L 2924/00013 (2013.01); H01L 2924/01029 (2013.01); H01L 2224/16237 (2013.01); H01L 2924/01327 (2013.01); H01L 24/33 (2013.01); H01L 2224/0401 (2013.01);
Abstract

A method for making an electronic device includes forming an interconnect layer stack on a rigid wafer substrate having a plurality of patterned electrical conductor layers, a dielectric layer between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer. An LCP solder mask having at least one aperture therein alignable with the at least one solder pad is formed. The LCP solder mask and interconnect layer stack are aligned and laminated together. Solder is positioned in the at least one aperture. At least one circuit component is attached to the at least one solder pad using the solder.


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