The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Oct. 11, 2011
Applicants:

Scott J. Alberhasky, Portland, OR (US);

David Harper, Battle Ground, WA (US);

Inventors:

Scott J. Alberhasky, Portland, OR (US);

David Harper, Battle Ground, WA (US);

Assignee:

Maxim Integrated Products, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823418 (2013.01); H01L 29/7835 (2013.01); H01L 29/4175 (2013.01); H01L 27/088 (2013.01); H01L 21/823475 (2013.01); H01L 21/823487 (2013.01);
Abstract

Semiconductor devices that include a trench with conductive material for connecting a VDMOS device to a LDMOS device are described. The semiconductor devices include a substrate having a first region and a second region, wherein the second region is disposed on the first region. A trench extends from a top surface of the second region to the first region. The semiconductor substrate includes a VDMOS device formed proximate to the top surface of the second region and a LDMOS device that is also formed proximate to the top surface of the second region. The drain region of the VDMOS device is electrically connected to the source region of the LDMOS device by way of a conductive material disposed in the trench.


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