The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Dec. 16, 2013
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Wataru Saito, Kanagawa, JP;

Syotaro Ono, Kanagawa, JP;

Shunji Taniuchi, Kanagawa, JP;

Miho Watanabe, Miyagi, JP;

Hiroaki Yamashita, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7839 (2013.01); H01L 29/0619 (2013.01); H01L 29/0623 (2013.01); H01L 29/0878 (2013.01); H01L 29/402 (2013.01); H01L 29/407 (2013.01); H01L 29/41741 (2013.01); H01L 29/41766 (2013.01); H01L 29/4236 (2013.01); H01L 29/42368 (2013.01); H01L 29/66727 (2013.01); H01L 29/66734 (2013.01); H01L 29/7806 (2013.01); H01L 29/7811 (2013.01); H01L 29/7813 (2013.01);
Abstract

A semiconductor device includes a first semiconductor layer of a first conductivity type. A second semiconductor layer of a second conductivity type is on the first semiconductor layer. A third semiconductor layer is on the second semiconductor layer. A fourth semiconductor layer is selectively in the first semiconductor layer. A first trench and second trench penetrate from a surface of the third layer through the second layer to reach the first layer. An embedded electrode is in the first trench. A control electrode is above the embedded electrode via an insulating film. A lower end of the second trench is connected to the fourth semiconductor layer. A first main electrode is electrically connected to the first layer. A second main electrode is provided in the second trench. A Schottky junction is formed by the first layer and the second main electrode at a sidewall of the second trench.


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