The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Nov. 19, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Robert K. Leidy, Burlington, VT (US);

Mark D. Levy, Milton, VT (US);

Qizhi Liu, Lexington, MA (US);

Gary L. Milo, Milton, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/73 (2006.01); H01L 29/737 (2006.01); H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7371 (2013.01); H01L 29/0649 (2013.01); H01L 29/66242 (2013.01); H01L 21/76232 (2013.01); H01L 21/30604 (2013.01);
Abstract

Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal. The asymmetry of the trench ensures that the trench isolation region has a relatively narrow width and, thereby ensures that both collector-to-base capacitance Cand collector resistance Rare minimized within the resulting bipolar semiconductor device.


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