The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2015
Filed:
Jun. 09, 2011
Yuji Ebiike, Tokyo, JP;
Takahiro Nakatani, Tokyo, JP;
Hiroshi Watanabe, Tokyo, JP;
Yoshio Fujii, Tokyo, JP;
Sunao Aya, Tokyo, JP;
Yoshiyuki Nakaki, Tokyo, JP;
Tsuyoshi Kawakami, Tokyo, JP;
Shuhei Nakata, Tokyo, JP;
Yuji Ebiike, Tokyo, JP;
Takahiro Nakatani, Tokyo, JP;
Hiroshi Watanabe, Tokyo, JP;
Yoshio Fujii, Tokyo, JP;
Sunao Aya, Tokyo, JP;
Yoshiyuki Nakaki, Tokyo, JP;
Tsuyoshi Kawakami, Tokyo, JP;
Shuhei Nakata, Tokyo, JP;
Mitsubishi Electric Corporation, Tokyo, JP;
Abstract
A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (d) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.