The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2015
Filed:
Sep. 12, 2012
Shin IL Choi, Hwaseong-si, KR;
Seung-ha Choi, Suwon-si, KR;
Bong-kyun Kim, Hwaseong-si, KR;
Sang Gab Kim, Seoul, KR;
Sho Yeon Kim, Yongin-si, KR;
Hyun Kim, Gunpo-si, KR;
Hong Sick Park, Suwon-si, KR;
Su Bin Bae, Gyeongsan-si, KR;
Shin Il Choi, Hwaseong-si, KR;
Seung-Ha Choi, Suwon-si, KR;
Bong-Kyun Kim, Hwaseong-si, KR;
Sang Gab Kim, Seoul, KR;
Sho Yeon Kim, Yongin-si, KR;
Hyun Kim, Gunpo-si, KR;
Hong Sick Park, Suwon-si, KR;
Su Bin Bae, Gyeongsan-si, KR;
SAMSUNG DISPLAY CO., LTD., , KR;
Abstract
A thin film transistor array panel according to an exemplary embodiment of the invention includes: a substrate; a gate line positioned on the substrate and including a gate electrode; a gate insulating layer positioned on the gate line; an oxide semiconductor layer positioned on the substrate; a source electrode and a drain electrode positioned on the oxide semiconductor layer; a first insulating layer positioned on the source electrode and the drain electrode and including a first contact hole; a data line positioned on the first insulating layer and intersecting the gate line; and a pixel electrode over the first insulating layer. The source electrode and the drain electrode each comprise a metal oxide. The data line is electrically connected to the source electrode through the first contact hole.