The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Sep. 07, 2012
Applicants:

Satoshi Nagashima, Mie-ken, JP;

Fumitaka Arai, Mie-ken, JP;

Hisataka Meguro, Mie-ken, JP;

Inventors:

Satoshi Nagashima, Mie-ken, JP;

Fumitaka Arai, Mie-ken, JP;

Hisataka Meguro, Mie-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/115 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11551 (2013.01); H01L 21/28273 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01); H01L 27/11524 (2013.01); H01L 29/42324 (2013.01); G11C 16/0408 (2013.01);
Abstract

A nonvolatile semiconductor memory device a first memory cell array layer, a first insulation layer formed on top of the first memory cell array layer, a second memory cell array layer formed on the first insulation layer, and a control gate. The first and second memory cell array layers have first and second NAND cell units provided with multiple first and second memory cells connected in series in a first direction and the first and second selection gates connected at both ends of the multiple first and second memory cells. The control gate is formed via an insulation layer between gates of the memory cells on both sides thereof in the first direction, and extends in the second direction perpendicular to the first direction.


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