The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Dec. 02, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Karl R. Erickson, Rochester, MN (US);

Phil C. Paone, Rochester, MN (US);

David P. Paulsen, Dodge Center, MN (US);

John E. Sheets, II, Zumbrota, MN (US);

Gregory J. Uhlmann, Rochester, MN (US);

Kelly L. Williams, Rochester, MN (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/088 (2006.01); G06F 17/50 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 21/8234 (2006.01); H01L 21/324 (2006.01); H01L 21/306 (2006.01); H01L 21/70 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); G06F 17/5045 (2013.01); H01L 29/7851 (2013.01); H01L 29/66803 (2013.01); H01L 29/4232 (2013.01); H01L 21/823431 (2013.01); H01L 21/823418 (2013.01); H01L 27/088 (2013.01); H01L 29/66553 (2013.01); H01L 21/324 (2013.01); H01L 21/30604 (2013.01);
Abstract

A method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with added device drive strength with buried field effect transistors (FETs) below and beside a traditional FinFET on a bulk substrate, and a design structure on which the subject circuit resides are provided. Buried field effect transistors (FETs) are formed on either side and under the traditional FinFET. The gate of the FinFET becomes the gate of the parallel buried (FETs) and allows self alignment to the underlying sources and drains of the buried FET devices in the bulk semiconductor.


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