The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Jun. 12, 2012
Applicants:

Luca Milani, Mairano, IT;

Kwangseok Han, Cambridge, GB;

Rainer Herberholz, Cambridge, GB;

Justin Penfold, Bury St. Edmunds, GB;

Inventors:

Luca Milani, Mairano, IT;

Kwangseok Han, Cambridge, GB;

Rainer Herberholz, Cambridge, GB;

Justin Penfold, Bury St. Edmunds, GB;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 19/08 (2006.01); G11C 17/18 (2006.01); G11C 16/04 (2006.01); G11C 29/02 (2006.01); G11C 29/00 (2006.01); H01L 27/112 (2006.01); G11C 17/14 (2006.01); G11C 29/04 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 17/18 (2013.01); G11C 16/0475 (2013.01); G11C 17/14 (2013.01); G11C 17/146 (2013.01); G11C 29/027 (2013.01); G11C 29/785 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/5006 (2013.01); H01L 27/11206 (2013.01);
Abstract

Control circuitry for memory cells is described. In an embodiment, a breakdown detection circuit is described which is arranged to detect abnormally high currents indicative of a defective cell during programming of a memory cell through monitoring the impedance level at a terminal in the breakdown detection circuit. The breakdown detection circuit is connected between the device being programmed and ground and comprises three transistors, at least one of which is capable of withstanding the programming voltage in case of breakdown. Other embodiments describe a flag bit cell design, a memory array and methods of reading and writing from/to that array, and circuitry for biasing a memory word-line for both read and write operations. The embodiments may be used separately or in a combination.


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