The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Jun. 21, 2013
Applicant:

4d-s, Ltd., Perth, AU;

Inventors:

Lee Cleveland, Santa Clara, CA (US);

Franz Michael Schuette, Colorado Springs, CO (US);

Assignee:

4D-S, LTD, Perth, AU;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 16/14 (2006.01); G11C 5/06 (2006.01); G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0097 (2013.01); G11C 13/0007 (2013.01); G11C 2213/71 (2013.01); G11C 2213/77 (2013.01); G11C 5/06 (2013.01); G11C 13/0002 (2013.01); G11C 5/02 (2013.01); G11C 5/025 (2013.01);
Abstract

A resistive random access memory integrated circuit for use as a mass storage media and adapted for bulk erase by substantially simultaneously switching all memory cells to one of at least two possible resistive states. Bulk switching is accomplished by biasing all bottom electrodes within an erase area to a voltage lower than that of the top electrodes, wherein the erase area can comprise the entire memory array of the integrated circuit or else a partial array. Alternatively the erase area may be a single row and, upon receiving the erase command, the row address is advanced automatically and the erase step is repeated until the entire array has been erased.


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