The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2015
Filed:
Jan. 09, 2014
Cavium, Inc., San Jose, CA (US);
Shahid Ikram, Shrewsbury, MA (US);
Isam Akkawi, Santa Clara, CA (US);
John Perveiler, Oxford, MA (US);
David Asher, Sutton, MA (US);
James Ellis, Hubbardston, MA (US);
CAVIUM, INC., San Jose, CA (US);
Abstract
A new approach is proposed that contemplates systems and methods to support a hybrid verification framework (HVF) to design, verify, and implement design protocols for an integrated circuit (IC) chip such as a system-on-chip (SOC) and/or an application-specific integrated circuit (ASIC) chip. The framework creates a plurality of specifications in form of extended state transition tables for different phases of a design flow of the IC chip. The framework integrates and uses the extended state table-based specifications and the templates in all phases in the design flow, resulting in a tight revision loop of debug, verification, and validation across the phases of the design flow.