The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Dec. 20, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

John T. Hollaway, Jr., Austin, TX (US);

Charles F. Marino, Round Rock, TX (US);

Praveen S. Reddy, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 12/08 (2006.01); G06F 1/04 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0831 (2013.01); G06F 1/04 (2013.01); G06F 2212/62 (2013.01); G06F 13/1652 (2013.01);
Abstract

One or more systems, devices, methods, and/or processes described can determine a maximum cache command rate of a processor unit. For example, an interface of the processor unit configured to be coupled to an interconnect of a multiprocessor system and configured such that a first portion of the interface provides a signal to a second portion of the interface, where the first portion of the interface operates utilizing a known frequency and the second portion of the interface operates utilizing a cache frequency of the processor unit; the second portion of the interface circulates the signal; the first portion of the interface receives the signal from the second portion of the interface; the first portion of the interface determines a cache command rate based on the known frequency, the frequency of the cache, and the signal; and the interface provides information indicating the cache command rate to the interconnect.


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