The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2015

Filed:

Aug. 23, 2011
Applicants:

Youhua Wang, Nan'an District, CN;

Junan Zhang, Nan'an District, CN;

Dongbing Fu, Nan'an District, CN;

Gangyi HU, Nan'an District, CN;

Jun Liu, Nan'an District, CN;

Ruzhang LI, Nan'an District, CN;

Guangbing Chen, Nan'an District, CN;

Inventors:

Youhua Wang, Nan'an District, CN;

Junan Zhang, Nan'an District, CN;

Dongbing Fu, Nan'an District, CN;

Gangyi Hu, Nan'an District, CN;

Jun Liu, Nan'an District, CN;

Ruzhang Li, Nan'an District, CN;

Guangbing Chen, Nan'an District, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/017 (2006.01); H03K 5/04 (2006.01); H03K 7/08 (2006.01); H03K 5/06 (2006.01); H03K 5/156 (2006.01);
U.S. Cl.
CPC ...
H03K 5/06 (2013.01); H03K 5/1565 (2013.01);
Abstract

The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.


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