The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2015

Filed:

Jul. 12, 2013
Applicant:

Triquint Semiconductor, Inc., Hillsboro, OR (US);

Inventor:

Paul Saunier, Dallas, TX (US);

Assignee:

TriQuint Semiconductor, Inc., Hillsboro, OR (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/778 (2013.01); H01L 21/02458 (2013.01); H01L 21/0254 (2013.01); H01L 29/402 (2013.01); H01L 29/41766 (2013.01); H01L 29/4236 (2013.01); H01L 29/42376 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/66462 (2013.01); H01L 29/7787 (2013.01); H01L 29/2003 (2013.01);
Abstract

Embodiments of the present disclosure describe structural configurations of an integrated circuit (IC) device such as a high electron mobility transistor (HEMT) switch device and method of fabrication. The IC device includes a buffer layer formed on a substrate, a channel layer formed on the buffer layer to provide a pathway for current flow in a transistor device, a spacer layer formed on the channel layer, a barrier layer formed on the spacer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) or gallium (Ga), a gate dielectric directly coupled with the spacer layer or the channel layer, and a gate formed on the gate dielectric, the gate being directly coupled with the gate dielectric. Other embodiments may also be described and/or claimed.


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