The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2015

Filed:

Jul. 10, 2009
Applicants:

Thomas Ernst, Morette, FR;

Gabriel Molas, Grenoble, FR;

Barbara DE Salvo, Montbonnot, FR;

Stephane Becu, Bethune, FR;

Inventors:

Thomas Ernst, Morette, FR;

Gabriel Molas, Grenoble, FR;

Barbara De Salvo, Montbonnot, FR;

Stephane Becu, Bethune, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/80 (2006.01); H01L 27/115 (2006.01); H01L 21/822 (2006.01); H01L 27/06 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/115 (2013.01); H01L 21/8221 (2013.01); H01L 27/0688 (2013.01); H01L 27/11568 (2013.01); H01L 27/11578 (2013.01); H01L 27/11582 (2013.01); H01L 27/1203 (2013.01);
Abstract

A microelectronic flash memory device including a plurality of memory cells including transistors fitted with a matrix of channels connecting a block of common source to a second block on which bit lines rest, the transistors also being formed by a plurality of gates including at least one gate material, including a first selection gate coating the channels, a plurality of control gates coating the channels, a plurality of second selection gates each coating the channels of the same row and the matricial arrangement, at least one or more of the gates based on superposition of layers including at least one first layer of dielectrical material, at least one charge store zone, and at least one second layer of dielectrical material.


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