The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2015

Filed:

Mar. 05, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Toshiaki Kirihata, Poughkeepsie, NY (US);

Phil C. Paone, Rochester, MN (US);

Vimal R. Patel, Rochester, MN (US);

Gregory J. Uhlmann, Rochester, MN (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01H 37/76 (2006.01); H01H 85/00 (2006.01); H01H 85/05 (2006.01);
U.S. Cl.
CPC ...
H01H 85/05 (2013.01);
Abstract

Embodiments may include an eFuse cell. The eFuse cell may include an eFuse having a first end and a second end. A blowFET has a first source/drain area, a second source/drain area, and a first gate. The first source/drain area is coupled to the second end of the eFuse, the second source/drain area is coupled to ground, and the first gate is coupled to a first node. The eFuse cell includes a senseFET having a third source/drain area, a fourth source/drain area, and a second gate. The second gate is coupled to the first node, and the third source/drain area is coupled to a second node. The second node is coupled to an operation signal and the second end of the eFuse. The eFuse cell includes a select eFuse logic element having an input to receive a select eFuse signal and an output coupled to the first node.


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