The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9053821 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 09, 2015

Filed:

Apr. 02, 2014
Applicant:

Ps4 Luxco S.a.r.l., Luxembourg, LU;

Inventors:

Yoshiro Riho, Tokyo, JP;

Hiromasa Noda, Tokyo, JP;

Kazuki Sakuma, Tokyo, JP;

Assignee:

PS4 Luxco S.a.r.l., Luxembourg, LU;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 29/00 (2006.01); G11C 29/06 (2006.01); G11C 29/12 (2006.01); G11C 29/28 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01); G11C 29/26 (2006.01);
U.S. Cl.
CPC ...
G11C 29/00 (2013.01); G11C 29/06 (2013.01); G11C 29/12005 (2013.01); G11C 29/28 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/2602 (2013.01); G11C 29/02 (2013.01); G11C 29/50 (2013.01);
Abstract

A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays, and each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at a time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent to each other in the plurality of memory cell mats. According to the present invention, the memory cell mats with the plurality of activated word lines are distributed. Therefore, as compared with many word lines activated in one memory cell mat, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced. As a result, more word lines can be activated at the same time.


Find Patent Forward Citations

Riho, Yoshiro. (2015). Semiconductor device performing stress test (U.S. Patent No. 9053821). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9053821

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