The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2015

Filed:

Dec. 05, 2013
Applicant:

Seiko Instruments Inc., Chiba, JP;

Inventors:

Ayako Kawakami, Chiba, JP;

Kazuhiro Tsumura, Chiba, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/12 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/12 (2013.01); G11C 16/0408 (2013.01);
Abstract

A non-volatile memory circuit is formed of a P-channel MOS transistor and includes a P-channel non-volatile memory element having a floating gate and a control gate capacitively coupled together. A resistor divider has a first resistor and a second resistor for dividing a voltage difference between a power supply voltage and a ground voltage. A divided voltage output of the resistor divider is connected to the control gate. First and second switches are connected in parallel to the respective first and second resistors. The first and second switches are controlled so that a voltage of the control gate is set to a voltage of the divided voltage output which maximizes an electric field between a pinch-off point and a drain point of the P-channel MOS transistor in a writing mode.


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