The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2015

Filed:

May. 06, 2014
Applicant:

Ps4 Luxco S.a.r.l., Luxembourg, LU;

Inventor:

Hideyuki Yokou, Tokyo, JP;

Assignee:

PS4 Luxco S.a.r.l., Luxembourg, LU;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 5/14 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); H05K 1/18 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G11C 5/14 (2013.01); G11C 5/06 (2013.01); G11C 7/10 (2013.01); H01L 25/00 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/15311 (2013.01); H05K 1/18 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); G11C 11/4074 (2013.01);
Abstract

To provide a semiconductor system including a plurality of core chips and an interface chip that controls the core chips. Each of the core chips includes an internal voltage generating circuit. The interface chip includes an unused chip information holding circuit that stores therein unused chip information of the core chips. The core chips respectively receive the unused chip information from the unused chip information holding circuit. When the unused chip information indicates an unused state, the internal voltage generating circuits are inactivated, and when the unused chip information indicates a used state, the internal voltage generating circuits are activated. With this configuration, unnecessary power consumption by the unused chips is reduced.


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