The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2015

Filed:

Mar. 26, 2012
Applicants:

Robert L. Horn, Yorba Linda, CA (US);

Sebastien A. Jean, Irvine, CA (US);

Inventors:

Robert L. Horn, Yorba Linda, CA (US);

Sebastien A. Jean, Irvine, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01);
Abstract

Disclosed herein is a controller architecture that pairs a controller with a NVM (non-volatile memory) storage system over a high-level, high speed interface such as PCIe. In one embodiment, the NVM storage system includes a bridge that communicates with the controller via the high-level interface, and controls the NVM via an interface. The controller is provided a rich set of physical level of controls over individual elements of the NVM. In one embodiment, the controller includes a volatile memory (e.g., DRAM) that stores parameters related to the operation of the NVM as provided by the bridge. The parameters may be related to optimizing use of the NVM and are automatically appended by the controller to appropriate data storage commands to the bridge. The parameters may be stored in a table format in which each entry is indexed by a physical address of the NVM.


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