The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2015

Filed:

Jun. 03, 2008
Applicants:

Ronald Hall, Cedar Park, TX (US);

Michael L. Karm, Cedar Park, TX (US);

Brian R. Mestan, Austin, TX (US);

David Mui, Round Rock, TX (US);

Inventors:

Ronald Hall, Cedar Park, TX (US);

Michael L. Karm, Cedar Park, TX (US);

Brian R. Mestan, Austin, TX (US);

David Mui, Round Rock, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/381 (2013.01); G06F 9/3814 (2013.01); G06F 9/3851 (2013.01);
Abstract

A design structure provides instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.


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