The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2015

Filed:

Jul. 29, 2014
Applicant:

Mediatek Singapore Pte. Ltd., Singapore, SG;

Inventors:

Siu-Chuang Ivan Lu, San Jose, CA (US);

George Chien, Saratoga, CA (US);

Yen-Horng Chen, Taipei, TW;

Chi-Yao Yu, Hsinchu County, TW;

Lan-Chou Cho, New Taipei, TW;

Chih-Chun Tang, Taipei, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/28 (2006.01); H04B 1/10 (2006.01); H04B 1/16 (2006.01); H03F 1/22 (2006.01); H03F 3/21 (2006.01); H03F 3/45 (2006.01); H03F 3/72 (2006.01); H04B 1/18 (2006.01); H03F 3/193 (2006.01);
U.S. Cl.
CPC ...
H04B 1/16 (2013.01); H03F 1/223 (2013.01); H03F 3/211 (2013.01); H03F 3/45188 (2013.01); H03F 3/45475 (2013.01); H03F 3/72 (2013.01); H03F 2203/45386 (2013.01); H03F 2203/7236 (2013.01); H04B 1/18 (2013.01); H04B 1/28 (2013.01); H03F 3/193 (2013.01); H03F 3/21 (2013.01); H03F 2200/165 (2013.01); H03F 2200/294 (2013.01); H03F 2200/451 (2013.01);
Abstract

One exemplary receiver for a wireless communication system includes signal processing components arranged to generate a receiver output according to a radio frequency (RF) signal. The signal processing components include amplifiers having a class-AB biased amplifier included therein. The signal processing components are disposed in a chip, and the class-AB biased amplifier is an amplifier which processes a signal corresponding to the RF signal before any other amplifier included in the chip. The class-AB biased amplifier has a first amplifier block, a bias circuit and a second amplifier block. The first amplifier block is arranged to receive an input at the input port and generating a first output. The bias circuit is arranged to bias the first amplifier block for a class-AB operation. The second amplifier block is arranged to generate an output at the output port according to the first output.


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