The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2015

Filed:

Mar. 18, 2014
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Mohammad Nizam U. Kabir, Tempe, AZ (US);

Brandt Braswell, Chandler, AZ (US);

Douglas A. Garrity, Gilbert, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 (2006.01); H03M 1/08 (2006.01); H03M 1/68 (2006.01); H03M 1/74 (2006.01);
U.S. Cl.
CPC ...
H03M 1/661 (2013.01); H03M 1/0863 (2013.01); H03M 1/68 (2013.01); H03M 1/742 (2013.01);
Abstract

A digital to analog converter including a current steering source and a master replica bias network. The current steering source includes a data current source providing a source current to a source node, a switch circuit operative to steer the source current to a selected one of first and second control nodes based on a data bit, a buffer circuit that buffers the source current between the first control node and a first current output node or between the second control node and a second current output node, and an activation current source provides activation current to the buffer circuit via the first and second control nodes. The master replica bias network replicates biasing of the buffer circuit relative to a replica control node and drives the buffer circuit to maintain the first control node, the second control node and the replica control node at a common master control voltage.


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