The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2015
Filed:
Aug. 18, 2011
Longxing Shi, Jiangsu, CN;
Danhong Gu, Jiangsu, CN;
Junhui Gu, Jiangsu, CN;
Jianhui Wu, Jiangsu, CN;
Wei Zhao, Jiangsu, CN;
Zhiyi YE, Jiangsu, CN;
Dahai HU, Jiangsu, CN;
Meng Zhang, Jiangsu, CN;
Hong LI, Jiangsu, CN;
Longxing Shi, Jiangsu, CN;
Danhong Gu, Jiangsu, CN;
Junhui Gu, Jiangsu, CN;
Jianhui Wu, Jiangsu, CN;
Wei Zhao, Jiangsu, CN;
Zhiyi Ye, Jiangsu, CN;
Dahai Hu, Jiangsu, CN;
Meng Zhang, Jiangsu, CN;
Hong Li, Jiangsu, CN;
SOUTHEAST UNIVERSITY, Jiangsu, CN;
Abstract
A high-speed fully differential clock duty cycle calibration circuit applied to calibrating the clock duty cycle in a high-speed system. The circuit detects the duty cycle with a continuous time integrator, and directly adjusts the duty cycle on a clock transmission link so as to increase the working speed. Being of a fully differential circuit structure, the circuit can calibrate the duty cycle under a designated process within a higher and wider frequency range, and has relatively good constraining force for process mismatch and common mode noise. The circuit comprises adjustment level ADJand ADJ, a first buffer level BUF, a second buffer level BUFand a duty cycle detection level DCD.