The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2015

Filed:

Mar. 20, 2014
Applicant:

Renesas Electronics Corporation, Kanagawa, JP;

Inventors:

Yasuaki Kagotoshi, Kanagawa, JP;

Koichi Arai, Kanagawa, JP;

Natsuki Yokoyama, Tokyo, JP;

Haruka Shimizu, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/337 (2006.01); H01L 21/00 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 29/808 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66893 (2013.01); H01L 29/66068 (2013.01); H01L 29/8083 (2013.01); H01L 29/1066 (2013.01); H01L 29/1608 (2013.01);
Abstract

A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n-type source layer on a surface of an n-type drift layer formed on an n-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n-type drift layer with a silicon oxide film formed on the n-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.


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