The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2015

Filed:

Sep. 12, 2012
Applicants:

Josephine B. Chang, Bedford Hills, NY (US);

Michael A. Guillorn, Yorktown Heights, NY (US);

Amlan Majumdar, White Plains, NY (US);

Lidija Sekaric, Arlington, VA (US);

Inventors:

Josephine B. Chang, Bedford Hills, NY (US);

Michael A. Guillorn, Yorktown Heights, NY (US);

Amlan Majumdar, White Plains, NY (US);

Lidija Sekaric, Arlington, VA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/265 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66772 (2013.01); H01L 29/785 (2013.01); H01L 29/78654 (2013.01);
Abstract

Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.


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