The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2015
Filed:
Jun. 04, 2013
Applicant:
Renesas Electronics Corporation, Kanagawa, JP;
Inventors:
Takamitsu Kanazawa, Kanagawa, JP;
Satoru Akiyama, Machida, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/60 (2006.01); H01L 27/088 (2006.01); H01L 29/16 (2006.01); H03K 3/012 (2006.01); H03K 17/10 (2006.01); H03K 17/567 (2006.01); H01L 29/78 (2006.01); H01L 23/495 (2006.01); H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0883 (2013.01); H01L 29/1608 (2013.01); H03K 3/012 (2013.01); H03K 17/102 (2013.01); H03K 17/107 (2013.01); H03K 17/567 (2013.01); H03K 2017/6875 (2013.01); H01L 29/7827 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49111 (2013.01); H01L 2924/30107 (2013.01); H01L 2924/3011 (2013.01); H01L 2924/13091 (2013.01);
Abstract
There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set in an OFF state.