The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2015
Filed:
Jun. 29, 2010
Yuancheng Christopher Pan, San Diego, CA (US);
Fifin Sweeney, San Diego, CA (US);
Lew G. Chua-eoan, San Diego, CA (US);
Zhi Zhu, San Diego, CA (US);
Junmou Zhang, San Diego, CA (US);
Yuancheng Christopher Pan, San Diego, CA (US);
Fifin Sweeney, San Diego, CA (US);
Lew G. Chua-Eoan, San Diego, CA (US);
Zhi Zhu, San Diego, CA (US);
Junmou Zhang, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.