The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2015

Filed:

May. 29, 2012
Applicants:

Vikash, Bangalore, IN;

Kamal Chandwani, Ahmedabad, IN;

Rahul Sahu, Kasganj-Kanshiram-Nagar, IN;

Inventors:

Vikash, Bangalore, IN;

Kamal Chandwani, Ahmedabad, IN;

Rahul Sahu, Kasganj-Kanshiram-Nagar, IN;

Assignee:

LSI CORPORATION, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 16/04 (2006.01); G11C 7/22 (2006.01); G11C 11/24 (2006.01); G11C 29/50 (2006.01); G11C 11/41 (2006.01);
U.S. Cl.
CPC ...
G11C 7/227 (2013.01); G11C 11/24 (2013.01); G11C 11/41 (2013.01); G11C 29/50012 (2013.01);
Abstract

A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises at least one dummy memory cell, a feedback-based controller having inputs coupled to respective internal nodes of the dummy memory cell, and write signal generation circuitry coupled to the feedback-based controller and configured to provide one or more write signals for controlling writing of data to portions of the memory array. The feedback-based controller generates a reset signal for application to a reset input of the write signal generation circuitry at least in part as a function of a logic level transition delay of a selected one of the first and second internal nodes of the dummy memory cell.


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