The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2015

Filed:

Feb. 15, 2012
Applicants:

Eric LI, Milpitas, CA (US);

Yutao Chen, Guangzhou, CN;

Jianxin Xue, Shanghai, CN;

Wenjie Yang, Guangzhou, CN;

Shoulin LI, Guangzhou, CN;

Chun LU, San Jose, CA (US);

Zhifeng Wen, Foshan, CN;

Shean-yih Chiou, San Jose, CA (US);

Shang-kuan Tang, Fremont, CA (US);

Shahnad Nadershahi, Simi Valley, CA (US);

Inventors:

Eric Li, Milpitas, CA (US);

Yutao Chen, Guangzhou, CN;

Jianxin Xue, Shanghai, CN;

Wenjie Yang, Guangzhou, CN;

Shoulin Li, Guangzhou, CN;

Chun Lu, San Jose, CA (US);

Zhifeng Wen, Foshan, CN;

Shean-Yih Chiou, San Jose, CA (US);

Shang-Kuan Tang, Fremont, CA (US);

Shahnad Nadershahi, Simi Valley, CA (US);

Assignee:

SCT TECHNOLOGY, LTD., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/32 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/32 (2013.01); G09G 2300/06 (2013.01); G09G 2310/0248 (2013.01); G09G 2310/0275 (2013.01); G09G 2330/025 (2013.01); G09G 2330/04 (2013.01);
Abstract

The present disclosure provides a circuit for discharging parasitic capacitance in a display panel with common-anode topology having a plurality of light emitters, as well as a circuit for charging parasitic capacitance in a display panel with common-cathode topology. In the common-cathode topology, the circuit includes a three-terminal device having a gate, a source, and a drain, wherein one of the source and the drain is electrically coupled to a common cathode of the light emitters, and a mechanism for controlling the three-terminal device, the mechanism being electrically coupled to the gate. Shortly after a previously selected light emitter is unselected, the mechanism turns on the three-terminal device to form a conductive path between the source and the drain. The mechanism turns off the three-terminal device after a voltage at the common cathode is increased to a predetermined voltage level or after a maximum period of time lapses.


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