The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2015

Filed:

Aug. 03, 2012
Applicants:

Qamrul Hasan, Santa Clara, CA (US);

Clifford Zitlaw, Chico, CA (US);

Stephan Rosner, Campbell, CA (US);

Sylvain Dubois, Antibes, FR;

Inventors:

Qamrul Hasan, Santa Clara, CA (US);

Clifford Zitlaw, Chico, CA (US);

Stephan Rosner, Campbell, CA (US);

Sylvain Dubois, Antibes, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 13/16 (2013.01); Y02B 60/1225 (2013.01);
Abstract

Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle.


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