The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2015

Filed:

Oct. 31, 2013
Applicant:

Shanghai Avic Optoelectronics Co., Ltd., Shanghai, CN;

Inventor:

Yanfeng Liang, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B44C 1/22 (2006.01); G02F 1/1343 (2006.01); H01L 21/02 (2006.01); B81C 1/00 (2006.01); H01L 31/18 (2006.01); G02F 1/1335 (2006.01); G02F 1/1333 (2006.01);
U.S. Cl.
CPC ...
G02F 1/13439 (2013.01); G02F 1/134363 (2013.01); H01L 21/02052 (2013.01); B81C 1/00539 (2013.01); H01L 31/1884 (2013.01); G02F 1/133516 (2013.01); G02F 2201/123 (2013.01); G02F 1/1333 (2013.01);
Abstract

A method of fabricating an In-Plane Switching (IPS) screen electrode is disclosed. In the method, a first ITO layer is etched, and the etched first ITO layer is annealed. Subsequently, a second ITO layer is etched, and the etched first ITO layer and the etched second ITO layer are concurrently annealed. With this method, the etched first ITO layer is annealed after the first ITO layer is etched, subsequent etching of the second ITO layer will have no influence upon the annealed first ITO layer, thus making it possible to ensure the line widths of the two ITO layers and a spacing between the respective ITO layers to thereby effectively avoid the problem of a short circuit due to a too small spacing between the respective ITO layers.


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