The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2015
Filed:
Feb. 28, 2012
Applicant:
Pascal Pavao, St-Jerome, CA;
Inventor:
Pascal Pavao, St-Jerome, CA;
Assignee:
KONINKLIJKE PHILIPS N.V., Eindhoven, NL;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/62 (2010.01); F21V 15/04 (2006.01); H01L 33/48 (2010.01); H05K 1/18 (2006.01); F21V 15/00 (2006.01); H05K 13/00 (2006.01);
U.S. Cl.
CPC ...
F21V 15/04 (2013.01); H01L 33/486 (2013.01); H05K 1/181 (2013.01); H05K 2201/10106 (2013.01); F21V 15/00 (2013.01); H05K 13/00 (2013.01);
Abstract
Methods and apparatus related to a circuit board having a dielectric layer (A/B,A/B,B,B) on the top and/or bottom thereof. A circuit board is provided having a core layer () and at least one conductive layer (A/B,A/B,A/B,A/B,) positioned on a first side of the core layer (). An outer dielectric layer (A/B,A/B,B,B) is provided atop an outermost of the at least one conductive layer (A/B,A/B,A/B,A/B,). The dielectric layer (A/B,A/B,B,B) includes a plurality of openings (A,A,A) that provide access to at least one of connection pads and vias that are in electrical contact with one or more of the conductive layer(s) (A/B,A/B,A/B,A/B,).