The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2015

Filed:

Jan. 29, 2010
Applicants:

Harvey J. Stiegler, Plano, TX (US);

Luan A. Dang, Richardson, TX (US);

Inventors:

Harvey J. Stiegler, Plano, TX (US);

Luan A. Dang, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/06 (2006.01); G11C 7/02 (2006.01);
U.S. Cl.
CPC ...
G11C 7/02 (2013.01); G11C 16/04 (2013.01); G11C 16/06 (2013.01);
Abstract

Memory architecture, such as for a flash EEPROM memory embedded within a processor or other large scale integrated circuit, and including differential sense circuitry. The memory includes an array of memory cells in rows and columns, and organized into sectors, each sector split into portions. Columns of the array are grouped into small groups from which a final stage column decode selects a column from the group based on the least significant bits of the column address. Adjacent groups of columns are paired, with a selected column from each group coupled to a differential input of the sense amplifier, but with one of the selected columns associated with an unselected sector portion and thus serving as a dummy bit line. Conductor routing is simplified, and chip area is reduced, by maintaining unselected column groups adjacent or nearby to selected column groups.


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