The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2015

Filed:

Sep. 14, 2012
Applicants:

Min Seok OH, Osan-si, KR;

Hae Kyung Kong, Yongin-si, KR;

Tae Chan Kim, Yongin-si, KR;

Jung Chak Ahn, Yongin-si, KR;

Moo Sup Lim, Yongin-si, KR;

Inventors:

Min Seok Oh, Osan-si, KR;

Hae Kyung Kong, Yongin-si, KR;

Tae Chan Kim, Yongin-si, KR;

Jung Chak Ahn, Yongin-si, KR;

Moo Sup Lim, Yongin-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 13/02 (2006.01); H01L 27/146 (2006.01); H04N 5/3745 (2011.01); G01S 7/486 (2006.01);
U.S. Cl.
CPC ...
H04N 13/0271 (2013.01); H01L 27/14656 (2013.01); H04N 5/37452 (2013.01); G01S 7/4863 (2013.01);
Abstract

A 3D image sensor includes a depth pixel that includes; a photo detector generating photo-charge, first and second floating diffusion regions, a first transfer transistor transferring photo-charge to the first floating diffusion region during a first transfer period in response to a first transfer gate signal, a second transfer transistor transferring photo-charge to the second floating diffusion region during a second transfer period in response to a second transfer gate signal, and an overflow transistor that discharges surplus photo-charge in response to a drive gate signal. Control logic unit controlling operation of the depth pixel includes a first logic element providing the first transfer gate signal, a second logic element providing the second transfer gate signal, and another logic element providing the drive gate signal to the overflow transistor when the first transfer period overlaps, at least in part, the second transfer period.


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