The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2015

Filed:

Jul. 24, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Horia Giuroiu, Campbell, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B 1/00 (2006.01); H03K 5/00 (2006.01); H04B 1/10 (2006.01); H03H 11/12 (2006.01); H04R 1/10 (2006.01); H04R 3/00 (2006.01); H04R 5/04 (2006.01);
U.S. Cl.
CPC ...
H03H 11/1217 (2013.01); H04R 1/1083 (2013.01); H04R 3/00 (2013.01); H04R 5/04 (2013.01); H04R 2460/01 (2013.01);
Abstract

An apparatus includes a biquad filter having first and second lossy integrators and multiple input networks. Each lossy integrator includes an amplifier, and each input network is coupled to an input of the amplifier in one of the lossy integrators. Each input network includes multiple resistors and a capacitor arranged in a T-structure. In a single-ended configuration, each input network includes a grounded capacitor. In a fully-differential configuration, each input network includes one of: a grounded capacitor and a floating capacitor coupled to another input network. The amplifiers and resistors could form a portion of an integrated circuit chip, which also includes multiple input/output pins. A single grounded capacitor could be coupled to a single input/output pin of the integrated circuit chip for an input network. A single floating capacitor could be coupled to two input/output pins of the integrated circuit chip for a pair of input networks.


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