The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2015
Filed:
Sep. 30, 2013
Applicant:
Cavium, Inc., San Jose, CA (US);
Inventors:
Scott Meninger, Groton, MA (US);
Rohan Arora, Marlborough, MA (US);
Assignee:
Cavium, Inc., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); G06F 1/06 (2006.01); H03L 7/08 (2006.01);
U.S. Cl.
CPC ...
G06F 1/06 (2013.01); H03L 7/08 (2013.01);
Abstract
A system on chip (SOC) includes a clock generator to provide one or more on-chip reference clocks to a number of physical medium attachments (PMAs) across a common clock bus. The clock generator receives one or more external, off-chip clock lines, from which it generates the on-chip reference clocks. Each of the PMAs may operate data input/output (I/O) channels under a variety of different communications protocols, which can have common or distinct reference clock frequencies. Accordingly, the on-chip reference clocks are generated to provide the required reference clocks to each of the PMAs.