The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2015

Filed:

Sep. 12, 2011
Applicants:

Shozo Ochi, Osaka, JP;

Kazuya Ushirokawa, Osaka, JP;

Keiichi Kusumoto, Hyogo, JP;

Takashi Yamada, Hyogo, JP;

Ken Yasue, Kyoto, JP;

Inventors:

Shozo Ochi, Osaka, JP;

Kazuya Ushirokawa, Osaka, JP;

Keiichi Kusumoto, Hyogo, JP;

Takashi Yamada, Hyogo, JP;

Ken Yasue, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 24/14 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 2224/1403 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/81193 (2013.01); H01L 2924/15311 (2013.01); H01L 24/05 (2013.01); H01L 25/18 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73207 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 23/49833 (2013.01); H01L 23/4985 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73265 (2013.01); H01L 24/80 (2013.01); H01L 23/49816 (2013.01);
Abstract

An implementing structure intermediate body including: a first chip having a first connection terminal; a second chip having a second connection terminal in a face that faces the first chip; and a film wiring substrate having a third connection terminal in one face, which is arranged between the first chip and the second chip, is loaded on a chip loading substrate having a fifth connection terminal so that another one face of the first chip is confronted thereby. In the film wiring substrate, there is a portion that is located outside any of the first chip and the second chip, at the tip part, is provided a fourth connection terminal connected to the third connection terminal by wiring, one part of the first connection terminal is connected with the second connection terminal, the third connection terminal is connected with another one part of the first connection terminal, and the fifth connection terminal is connected to the fourth connection terminal.


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