The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2015

Filed:

May. 31, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Christian Lavoie, Pleasantville, NY (US);

Effendi Leobandung, Stormville, NY (US);

Dan Moy, Bethel, CT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/306 (2006.01); H01L 21/283 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 28/00 (2013.01); H01L 21/283 (2013.01); H01L 21/306 (2013.01);
Abstract

A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes an enhanced performance electrical fuse formed in a polysilicon fin using a trench silicide process. In one embodiment, at least one semiconductor fin is formed on a dielectric layer present on the surface of a semiconductor substrate. An isolation layer may be formed over the exposed portions of the dielectric layer and the at least one semiconductor fin. At least two contact vias may be formed through the isolation layer to expose the top surface of the semiconductor fin. A continuous silicide may be formed on and substantially below the exposed surfaces of the semiconductor fin extending laterally at least between the at least two contact vias to form an electronic fuse (eFuse). In another embodiment, the at least one semiconductor fin may be subjected to ion implantation to facilitate the formation of silicide.


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