The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2015

Filed:

Jun. 22, 2012
Applicant:

Joel M. Mcgregor, San Jose, CA (US);

Inventor:

Joel M. McGregor, San Jose, CA (US);

Assignee:

Monolithic Power Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/402 (2013.01); H01L 29/66659 (2013.01); H01L 29/66719 (2013.01); H01L 29/7816 (2013.01); H01L 29/7835 (2013.01); H01L 29/0619 (2013.01); H01L 29/0634 (2013.01); H01L 29/0692 (2013.01); H01L 29/0696 (2013.01); H01L 29/0847 (2013.01); H01L 29/086 (2013.01); H01L 29/0878 (2013.01);
Abstract

The present disclosure discloses a lateral transistor and associated method for making the same. The lateral transistor comprises a gate formed over a first portion of a thin gate dielectric layer, and a field plate formed over a thick field dielectric layer and extending atop a second portion of the thin gate dielectric layer. The field plate is electrically isolated from the gate by a gap overlying a third portion of the thin gate dielectric layer and is electrically coupled to a source region. The lateral transistor according to an embodiment of the present invention may have reduced gate-to-drain capacitance, low specific on-resistance, and improved hot carrier lifetime.


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