The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2015

Filed:

Jan. 10, 2012
Applicants:

Toshitaka Miyata, Yokohama, JP;

Kanna Adachi, Chigasaki, JP;

Shigeru Kawanaka, Yokohama, JP;

Inventors:

Toshitaka Miyata, Yokohama, JP;

Kanna Adachi, Chigasaki, JP;

Shigeru Kawanaka, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/16 (2006.01); H01L 29/772 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/772 (2013.01); H01L 29/0895 (2013.01); H01L 29/1054 (2013.01); H01L 29/1608 (2013.01); H01L 29/165 (2013.01); H01L 29/6656 (2013.01); H01L 29/7836 (2013.01);
Abstract

According to one embodiment, a semiconductor device including: a substrate; a gate electrode formed above the substrate; a gate insulating film formed under the gate electrode; a channel layer formed under the gate insulating film by using a channel layer material; a source region and a drain region formed in the substrate so as to interpose the channel layer therebetween in a channel direction; and a source extension layer formed in the substrate between the channel layer and the source region so as to overlap a source-side end portion of the channel layer. The source extension layer forms a heterointerface with the channel layer. The heterointerface is a tunnel channel for carries.


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