The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2015

Filed:

Sep. 07, 2014
Applicant:

Princeton Optronics Inc., Mercerville, NJ (US);

Inventors:

Qing Wang, Plainsboro, NJ (US);

Jean-Francois Seurin, Princeton Junction, NJ (US);

Chuni Lal Ghosh, West Windsor, NJ (US);

Laurence Watkins, Pennington, NJ (US);

Assignee:

Princeton Optronics Inc., Mercerville, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B23K 31/02 (2006.01); H01S 5/022 (2006.01); H01S 5/00 (2006.01); B23K 1/00 (2006.01);
U.S. Cl.
CPC ...
H01S 5/02272 (2013.01); H01S 5/0042 (2013.01); B23K 1/0016 (2013.01); B23K 2001/12 (2013.01);
Abstract

A process to bond VCSEL arrays to submounts and printed circuit boards is provided. The process is particularly suited to large area thin and ultra-thin VCSEL arrays susceptible to bending and warping. The process integrates a flatness measurement step and applying appropriate combination of pressure prior to bonding the VCSEL array to the submount or a printed circuit using a vacuum flux-less bonding process. The process is very promising in making very good quality bonding between the VCSEL array and a submount or a printed circuit board. The process is applied to construct optical modules with improved flatness that may be integrated with other electronic components in constructing optoelectronic systems.


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