The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2015

Filed:

Mar. 01, 2012
Applicants:

Rajat Phull, Monmouth Junction, NJ (US);

Srihari Cadambi, Princeton Junction, NJ (US);

Nishkam Ravi, Lawrenceville, NJ (US);

Srimat Chakradhar, Manalapan, NJ (US);

Inventors:

Rajat Phull, Monmouth Junction, NJ (US);

Srihari Cadambi, Princeton Junction, NJ (US);

Nishkam Ravi, Lawrenceville, NJ (US);

Srimat Chakradhar, Manalapan, NJ (US);

Assignee:

NEC Laboratories America, Inc., Princeton, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); G06F 9/46 (2006.01); G06F 9/50 (2006.01); G06F 9/52 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5083 (2013.01); G06F 9/522 (2013.01); G06F 9/5088 (2013.01);
Abstract

Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment.


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