The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2015
Filed:
Aug. 29, 2012
Applicant:
Angel Socarras, Lake Mary, FL (US);
Inventor:
Angel Socarras, Lake Mary, FL (US);
Assignee:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G01R 31/3185 (2006.01); G01R 31/3183 (2006.01); G01R 31/3177 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31718 (2013.01); G01R 31/318569 (2013.01); G01R 31/3183 (2013.01); G01R 31/318555 (2013.01); G01R 31/318558 (2013.01); G01R 31/318583 (2013.01); G01R 31/318544 (2013.01); G01R 31/318566 (2013.01); G01R 31/318533 (2013.01); G01R 31/3177 (2013.01); G11C 29/88 (2013.01); G11C 29/883 (2013.01); G01R 31/31707 (2013.01);
Abstract
Provided is an apparatus including a scheduler and a plurality of logic devices coupled to the scheduler, each including a defect indicator. The scheduler determines whether one or more of the logic devices is defective based upon its respective defect indicator. The scheduler intentionally omits sending workloads to the disabled logic units, and thus enables the device to be functional albeit at a lower performance or in a differently performing product.