The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2015

Filed:

Jan. 02, 2013
Applicants:

Bendik Kleveland, Santa Clara, CA (US);

Dipak K Sikdar, Santa Clara, CA (US);

Rajesh Chopra, San Ramon, CA (US);

Jay Patel, Los Gatos, CA (US);

Inventors:

Bendik Kleveland, Santa Clara, CA (US);

Dipak K Sikdar, Santa Clara, CA (US);

Rajesh Chopra, San Ramon, CA (US);

Jay Patel, Los Gatos, CA (US);

Assignee:

MoSys, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/20 (2006.01); G11C 29/44 (2006.01); G11C 29/16 (2006.01); G06F 11/10 (2006.01); G11C 29/12 (2006.01); G11C 29/06 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2094 (2013.01); G11C 29/44 (2013.01); G11C 29/4401 (2013.01); G11C 29/06 (2013.01); G11C 29/16 (2013.01); G11C 2029/0409 (2013.01); G06F 11/106 (2013.01); G11C 29/12 (2013.01);
Abstract

A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks.


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