The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2015
Filed:
Jan. 29, 2013
Devices and methods using supervisor chips (integrated circuits) to generate time acceptance windows
Applicant:
The United States of America As Represented BY the Secretary of the Navy, Washington, DC (US);
Inventors:
Deric Keith Mason, Ridgecrest, CA (US);
Michael David Haddon, Ridgecrest, CA (US);
Assignee:
The United States of America as Represented by the Secretary of the Navy, Washington, DC (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); F23Q 7/02 (2006.01); H03K 3/01 (2006.01); F42C 15/00 (2006.01);
U.S. Cl.
CPC ...
H03K 3/01 (2013.01); F42C 15/00 (2013.01); G06F 1/00 (2013.01);
Abstract
Timing circuits including supervisor chip(s), capacitors, and latches. The supervisor chip(s) and capacitors cooperate to generate an electrical signal (window signal) having a high logic state when the window is open. The latches are used to determine whether an event of interest occurred while the window was open using the generated window signal and an electrical signal asserted upon occurrence of the event of interest.