The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2015

Filed:

Jul. 26, 2012
Applicants:

Richard V DE Caro, El Dorado Hills, CA (US);

Danut Manea, Saratoga, CA (US);

Yongliang Wang, Saratoga, CA (US);

Stephen Trinh, San Jose, CA (US);

Paul Hill, Southampton, GB;

Inventors:

Richard V De Caro, El Dorado Hills, CA (US);

Danut Manea, Saratoga, CA (US);

Yongliang Wang, Saratoga, CA (US);

Stephen Trinh, San Jose, CA (US);

Paul Hill, Southampton, GB;

Assignee:

Artemis Acquisition LLC, Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/32 (2006.01); G11C 5/14 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3275 (2013.01); G06F 1/3206 (2013.01); G06F 1/3203 (2013.01); G06F 1/3287 (2013.01); G11C 5/147 (2013.01); G11C 5/148 (2013.01); G11C 16/30 (2013.01); G11C 2216/30 (2013.01); Y02B 60/32 (2013.01); Y02B 60/1228 (2013.01);
Abstract

A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.


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